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?2004 silicon storage technology, inc. s71267-00-000 7/04 1 the sst logo and superflash are registered trademarks of silicon storage technology, inc. mpf+ and combomemory are trademarks of silicon storage technology, inc. these specifications are subject to change without notice. preliminary specifications features: ? combomemories organized as: ? sst32hf162c: 1m x16 flash + 128k x16 sram ? sst32hf164c: 1m x16 flash + 256k x16 sram ? sst32hf324c: 2m x16 flash + 256k x16 sram single 2.7-3.3v read and write operations concurrent operation ? read from or write to sram while erase/program flash superior reliability ? endurance: 100,000 cycles (typical) ? greater than 100 years data retention low power consumption: ? active current: 15 ma (typical) for flash or sram read ? standby current: - sst32hfx1c: 12 a (typical) flexible erase capability ? uniform 2 kword sectors ? uniform 32 kword size blocks erase-suspend/erase-resume capabilities fast read access times: ? flash: 70 ns ?sram: 70 ns latched address and data for flash flash fast erase and word-program: ? sector-erase time: 18 ms (typical) ? block-erase time: 18 ms (typical) ? chip-erase time: 40 ms (typical) ? word-program time: 7 s (typical) flash automatic erase and program timing ? internal v pp generation flash end-of-write detection ? toggle bit ? data# polling cmos i/o compatibility jedec standard command set package available ? 48-ball lbga (10mm x 12mm x 1.4mm) product description the sst32hf16xc/324c combomemory devices inte- grate a cmos flash memory bank with a cmos sram memory bank in a multi-chip package (mcp), manufac- tured with sst?s proprietary, high performance super- flash technology. featuring high performance word-program, the flash memory bank provides a maximum word-program time of 7 sec. to protect against inadvertent flash write, the sst32hf16xc/324c devices c ontain on-chip hardware and software data protection schemes. the sst32hf16xc/324c devices offer a guaranteed endur- ance of 10,000 cycles. data retention is rated at greater than 100 years. the sst32hf16xc/324c devices consist of two indepen- dent memory banks with respective bank enable signals. the flash and sram memory banks are superimposed in the same memory address space. both memory banks share common address lines, data lines, we# and oe#. the memory bank selection is done by memory bank enable signals. the sram bank enable signal, bes# selects the sram bank. the flash memory bank enable signal, bef# selects the flash memory bank. the we# sig- nal has to be used with software data protection (sdp) command sequence when controlling the erase and pro- gram operations in the flash memory bank. the sdp com- mand sequence protects the data stored in the flash memory bank from accidental alteration. the sst32hf16xc/324c provide the added functionality of being able to simultaneously read from or write to the sram bank while erasing or programming in the flash memory bank. the sram memory bank can be read or written while the flash memory bank performs sector- erase, bank-erase, or word-program concurrently. all flash memory erase and prog ram operations will automati- cally latch the input address and data signals and complete the operation in background without further input stimulus requirement. once the internally controlled erase or pro- gram cycle in the flash bank has commenced, the sram bank can be accessed for read or write. multi-purpose flash plus + sram combomemory sst32hf162c / sst32hf164c / sst32hf324c sst32hf324 / 32832mb flash + 4mb sram, 32mb flash + 8mb sram (x16) mcp combomemories
2 preliminary specifications multi-purpose flash plus + sram combomemory sst32hf162c / sst32h f164c / sst32hf324c ?2004 silicon storage technology, inc. s71267-00-000 7/04 the sst32hf16xc/324c devices are suited for applica- tions that use both flash memory and sram memory to store code or data. for system s requiring low power and small form factor, the sst32hf16xc/324c devices sig- nificantly improve performance and reliability while lower- ing power consumption when compared with multiple chip solutions. the sst32hf16xc/324c inherently use less energy during erase and program operations than alternative flash technologies. the total energy con- sumed is a function of the applied voltage, current, and time of application. since, for any given voltage range, superflash technology uses less current to program and has a shorter erase time, the total energy consumed dur- ing any erase or program operation is less than alterna- tive flash technologies. superflash technology provides fixed erase and program times independent of the number of erase/program cycles that have occurred. therefore the system software or hard- ware does not have to be modified or de-rated as is neces- sary with alternative flash technologies, whose erase and program times increase with accumulated erase/program cycles. device operation the combomemory uses bes# and bef# to control oper- ation of either the sram or the flash memory bank. when bes# is low, the sram bank is activated for read and write operation. when bef# is low the flash bank is acti- vated for read, program or erase operation. bes# and bef# cannot be at low level at the same time. if bes# and bef# are both asserted to low level bus contention will result and the device may suffer permanent damage. all address, data, and control lines are shared by sram bank and flash bank which mi nimizes power consumption and loading. the device goes into standby when both bank enables are high. concurrent read/write operation the sst32hf16xc/324c provide the unique benefit of being able to read from or write to sram, while simulta- neously erasing or programming the flash. this allows data alteration code to be executed from sram, while altering the data in flash. see figure 21 for a flowchart. the follow- ing table lists all valid states. the device will ignore all sdp commands when an erase or program operation is in progress. note that product identification commands use sdp; therefore, these com- mands will also be ignored while an erase or program operation is in progress. flash read operation the read operation of the sst32hf16xc/324c devices is controlled by bef# and oe#. both have to be low, with we# high, for the system to obtain data from the outputs. bef# is used for flash memory bank selection. when bef# is high, the chip is deselected and only standby power is consumed. oe# is t he output control and is used to gate data from the output pins. the data bus is in high impedance state when oe# is high. refer to figure 5 for further details. c oncurrent r ead /w rite s tate t able flash sram program/erase read program/erase write
preliminary specifications multi-purpose flash plus + sram combomemory sst32hf162c / sst32hf164c / sst32hf324c 3 ?2004 silicon storage technology, inc. s71267-00-000 7/04 flash word-program operation the flash memory bank of the sst32hf16xc/324c devices is programmed on a word-by-word basis. before program operations, the memory must be erased first. the program operation consists of three steps. the first step is the three-byte load sequence for software data protection. the second step is to load word address and word data. during the word-program operation, the addresses are latched on the falling edge of either bef# or we#, which- ever occurs last. the data is latched on the rising edge of either bef# or we#, whichever occurs last. the third step is the internal program operation which is initiated after the rising edge of the fourth we# or bef#, whichever occurs first. the program operation, once initiated, will be com- pleted, within 10 s. see figures 6 and 7 for we# and bef# controlled program operation timing diagrams and figure 17 for flowcharts. during the program operation, the only valid flash read operat ions are data# polling and tog- gle bit. during the internal program operation, the host is free to perform additional tasks. any sdp commands loaded during the internal program operation will be ignored. flash sector/block- erase operation the flash sector/block-erase operation allows the system to erase the device on a sector-by-sector (or block-by- block) basis. the sst32hf16xc/324c offer both sector- erase and block-erase mode. the sector architecture is based on uniform sector size of 2 kword. the block-erase mode is based on uniform block size of 32 kword. the sector-erase operation is initiated by executing a six-byte command sequence with sector-erase command (30h) and sector address (sa) in the last bus cycle. the address lines a ms -a 11 are used to determine the sector address. the block-erase operation is initiated by executing a six- byte command sequence with block-erase command (50h) and block address (ba) in the last bus cycle. the address lines a ms -a 15 are used to determine the block address. the sector or block address is latched on the fall- ing edge of the sixth we# pulse, while the command (30h or 50h) is latched on the rising edge of the sixth we# pulse. the internal erase operation begins after the sixth we# pulse. the end-of-erase operation can be deter- mined using either data# polling or toggle bit methods. see figures 11 and 12 for timing waveforms. any com- mands issued during the sector- or block-erase operation are ignored. erase-suspend/erase-resume commands the erase-suspend operation temporarily suspends a sector- or block-erase operation thus allowing data to be read from any memory location, or program data into any sector/block that is not suspended for an erase operation. the operation is executed by issuing one byte command sequence with erase-suspend command (b0h). the device automatically enters read mode typically within 20 s after the erase-suspend command had been issued. valid data can be read from any sector or block that is not suspended from an erase operation. reading at address location within erase-suspended sectors/blocks will output dq 2 toggling and dq 6 at ?1?. while in erase-suspend mode, a word-program operation is allowed except for the sector or block selected for erase-suspend. to resume sector-erase or block-erase operation which has been suspended the system must issue erase resume command. the operation is executed by issuing one byte command sequence with erase resume command (30h) at any address in the last byte sequence. flash chip-erase operation the sst32hf16xc/324c provide a chip-erase opera- tion, which allows the user to erase the entire memory array to the ?1? state. this is useful when the entire device must be quickly erased. the chip-erase operation is initiated by executing a six- byte command sequence with chip-erase command (10h) at address 5555h in the last byte sequence. the erase operation begins with the rising edge of the sixth we# or bef#, whichever occurs first. during the erase operation, the only valid read is toggle bit or data# polling. see table 5 for the command sequence, figure 9 for tim- ing diagram, and figure 20 for the flowchart. any com- mands issued during the chip-erase operation are ignored. write operation status detection the sst32hf16xc/324c provide two software means to detect the completion of a write (program or erase) cycle, in order to optimize the system write cycle time. the soft- ware detection includes two status bits: data# polling (dq 7 ) and toggle bit (dq 6 ). the end-of-write detection mode is enabled after the rising edge of we#, which ini- tiates the internal program or erase operation.
4 preliminary specifications multi-purpose flash plus + sram combomemory sst32hf162c / sst32h f164c / sst32hf324c ?2004 silicon storage technology, inc. s71267-00-000 7/04 the actual completion of the nonvolatile write is asynchro- nous with the system; therefore, either a data# polling or toggle bit read may be simultaneous with the completion of the write cycle. if this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to con- flict with either dq 7 or dq 6. in order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. if both reads are valid, then the device has completed the write cycle, otherwise the rejec- tion is valid. flash data# polling (dq 7 ) when the sst32hf16xc/324c flash memory banks are in the internal program operation, any attempt to read dq 7 will produce the complement of the true data. once the program operation is completed, dq 7 will produce true data. note that even though dq 7 may have valid data immediately following the completion of an internal write operation, the remaining data outputs may still be invalid: valid data on the entire dat a bus will appear in subsequent successive read cycles after an interval of 1 s. during internal erase operation, any attempt to read dq 7 will pro- duce a ?0?. once the internal erase operation is completed, dq 7 will produce a ?1?. the data# polling is valid after the rising edge of the fourth we# (or bef#) pulse for program operation. for sector- or block-erase, the data# polling is valid after the rising edge of the sixth we# (or bef#) pulse. see figure 8 for data# polling timing diagram and figure 18 for a flowchart. toggle bits (dq6 and dq2) during the internal program or erase operation, any con- secutive attempts to read dq 6 will produce alternating ?1?s and ?0?s, i.e., toggling between 1 and 0. when the internal program or erase operation is completed, the dq 6 bit will stop toggling. the device is then ready for the next opera- tion. for sector-, block-, or chip-erase, the toggle bit (dq 6 ) is valid after the rising edge of sixth we# (or bef#) pulse. dq 6 will be set to ?1? if a read operation is attempted on an erase-suspended sector/block. if program operation is ini- tiated in a sector/block not selected in erase-suspend mode, dq 6 will toggle. an additional toggle bit is available on dq 2 , which can be used in conjunction with dq 6 to check whether a particular sector is being actively erased or erase-suspended. table 1 shows detailed status bits information. the toggle bit (dq 2 ) is valid after the rising edge of the last we# (or bef#) pulse of write operation. see figure 9 for toggle bit timing diagram and figure 18 for a flowchart. note: dq 7 and dq 2 require a valid address when reading status information. flash memory data protection the sst32hf16xc/324c flas h memory bank provides both hardware and software features to protect nonvolatile data from inadvertent writes. flash hardware data protection noise/glitch protection : a we# or bef# pulse of less than 5 ns will not initiate a write cycle. v dd power up/down detection: the write operation is inhibited when v dd is less than 1.5v. write inhibit mode: forcing oe# low, bef# high, or we# high will inhibit the flash write operation. this prevents inadvertent writes during power-up or power-down. flash software data protection (sdp) the sst32hf16xc/324c provide the jedec approved software data protection scheme for all flash memory bank data alteration operations, i.e., program and erase. any program operation requires the inclusion of a series of three-byte sequence. the three byte-load sequence is used to initiate the program operation, providing optimal protection from inadvertent write operations, e.g., during the system power-up or power-down. any erase operation requires the inclusion of six-byte load sequence. the sst32hf16xc/324c devices are shipped with the soft- ware data protection permanently enabled. see table 5 for the specific software command codes. during sdp com- mand sequence, invalid comm ands will abort the device to read mode, within t rc. the contents of dq 15 -dq 8 can be v il or v ih, but no other value, during any sdp command sequence. table 1: w rite o peration s tatus status dq 7 dq 6 dq 2 normal operation standard program dq 7 # toggle no toggle standard erase 0 toggle toggle erase- suspend mode read from erase-suspended sector/block 1 1 toggle read from non- erase-suspended sector/block data data data program dq 7 # toggle n/a t1.0 1267
preliminary specifications multi-purpose flash plus + sram combomemory sst32hf162c / sst32hf164c / sst32hf324c 5 ?2004 silicon storage technology, inc. s71267-00-000 7/04 sram read the sram read operation of the sst32hf16xc/324c is controlled by oe# and bes#, both have to be low with we# high for the system to obtain data from the outputs. bes# is used for sram bank selection. oe# is the output control and is used to gate data from the output pins. the data bus is in high impedance state when oe# is high. refer to the read cycle timing diagram, figure 2, for further details. sram write the sram write operation of the sst32hf16xc/324c is controlled by we# and bes#; both have to be low for the system to write to the sram. during the word-write oper- ation, the addresses and data are referenced to the rising edge of either bes# or we#, whichever occurs first. the write time is measured fr om the last falling edge of bes# or we# to the first rising edge of bes# or we#. refer to the write cycle timing diagrams, figures 3 and 4, for further details. product identification the product identification mode identifies the devices as the sst32hf16xc/324c and manufacturer as sst. this mode may be accessed by software operations only. the hardware device id read operation, which is typi- cally used by programmers, cannot be used on this device because of the shared lines between flash and sram in the multi-chip package. therefore, applica- tion of high voltage to pin a 9 may damage this device. users may use the software product identification opera- tion to identify the part (i.e., using the device id) when using multiple manufacturers in the same socket. for details, see tables 4 and 5 for software operation, figure 13 for the software id entry and read timing diagram and figure 19 for the id entry command sequence flowchart. product identificatio n mode exit/reset in order to return to the standard read mode, the software product identification mode must be exited. exiting is accomplished by issuing the exit id command sequence, which returns the device to the read operation. please note that the software reset command is ignored during an internal program or erase operation. this command may also be used to reset the device to read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g. not read correctly. see table 5 for software command codes, figure 14 for timing waveform and figure 19 for a flowchart. design considerations sst recommends a high frequency 0.1 f ceramic capac- itor to be placed as close as possible between v dd and v ss , e.g., less than 1 cm away from the v dd pin of the device. additionally, a low frequency 4.7 f electrolytic capacitor from v dd to v ss should be placed within 1 cm of the v dd pin. table 2: p roduct i dentification address data manufacturer?s id 0000h bfh device id sst32hf162c 0001h 234bh sst32hf164c 0001h 234bh sst32hf324c 0001h 235bh t2.0 1267
6 preliminary specifications multi-purpose flash plus + sram combomemory sst32hf162c / sst32h f164c / sst32hf324c ?2004 silicon storage technology, inc. s71267-00-000 7/04 i/o buffers 1267 b1.0 address buffers dq 15 - dq 8 a ms (1) -a 0 we# superflash memory sram control logic bes# bef# oe# address buffers & latches lbs# ubs# dq 7 - dq 0 f unctional b lock d iagram
preliminary s p ecific ations multi-purpose flash plus + sram combomemor y sst32h f162c / sst 32h f164c / sst 32hf 324c 7 ? 2 00 4 s i l i c on st or ag e te chno l o g y , in c. s7 12 67- 0 0 - 0 0 0 7 / 04 figure 1 : p in a ss ig nme n ts fo r 48- ba l l lbga (10 mm x 12 mm ) t able 3 : p in d es crip t ion symb ol pin name fu nctio n s a ms 1 -a 0 1. a ms =most significant a ddress ad dress in puts t o pro v ide flash a ddresses: a 19 -a 0 f o r 16m and a 20 -a 0 f o r 32m sram addresses: a 16 -a 0 f o r 2m and a 17 -a 0 fo r 4 m dq 15 -dq 0 d a ta inp u t/o u tput t o outpu t data du r i ng re ad cyc l e s and recei v e inp u t da ta d u r i n g wr ite cycles . data is inter n ally latched dur i ng a flash er ase/prog r a m cycle . the outputs are in tr i-state when oe# or bes# and be f# are high. bes# sra m memor y bank enab le t o activ a te the sram memor y bank when bes# is lo w . bef# f la sh memo r y ba nk en ab le t o activ a te th e fl ash me mor y ban k wh en bef# is lo w . oe# o utpu t enab le t o gate the data outpu t b u ff e r s . w e # w r i te enab le t o control the wr i t e op er a t i ons . v dd f p o wer su pply (fl a sh) 2 .7-3 .3 v p o w e r sup p ly to f l ash on ly . v dds p o w e r sup p l y (sr a m) 2. 7 - 3. 3v p o w e r su pp l y t o sr am o n l y v ss groun d ubs# u pper byte c ontrol (sram) t o ena b l e dq 15 -dq 8 lbs# l o w e r byte control (sram) t o ena b l e dq 7 -dq 0 nc n o conn ecti on un conne cte d pi ns t3. 0 12 67 bes# a10 oe# a11 a13 we# v ss dq5 dq7 a8 a17 v dds dq1 dq2 dq4 a5 ubs# a16 a1 a0 dq0 dq8 bef# v ss a2 a3 a6 dq3 dq10 dq9 a4 a7 a18 dq12 v ddf dq11 a19 nc nc a12 dq6 dq13 a9 a14 a15 lbs# dq15 dq14 a b c d e f g h sst32hf162c/sst32hf164c 6 5 4 3 2 1 t o p view (balls f acing do wn) 1267 48-lbga p1.0 bes# a10 oe# a11 a13 we# v ss dq5 dq7 a8 a17 v dds dq1 dq2 dq4 a5 ubs# a16 a1 a0 dq0 dq8 bef# v ss a2 a3 a6 dq3 dq10 dq9 a4 a7 a18 dq12 v ddf dq11 a19 a20 nc a12 dq6 dq13 a9 a14 a15 lbs# dq15 dq14 a b c d e f g h sst32hf324c 6 5 4 3 2 1 t o p view (balls f acing do wn) 1267 48-lbga p2.0
8 preliminary specifications multi-purpose flash plus + sram combomemory sst32hf162c / sst32h f164c / sst32hf324c ?2004 silicon storage technology, inc. s71267-00-000 7/04 table 4: o peration m odes s election mode bes# 1 bef# 1 oe# we# ubs# lbs# dq 15 to dq 8 dq 7 to dq 0 address not allowed v il v il x 2 xx x x x x flash read v ih v il v il v ih xx d out d out a in program v ih v il v ih v il xx d in d in a in erase x v il v ih v il x x x x sector or block address, xxh for chip-erase sram read v il v ih v il v ih v il v il d out d out a in v il v ih v il v ih v il v ih d out high z a in v il v ih v il v ih v ih v il high z d out a in write v il v ih xv il v il v il d in d in a in v il v ih xv il v il v ih d in high z a in v il v ih xv il v ih v il high z d in a in standby v ihc v ihc x x x x high z high z x flash write inhibit x x v il x x x high z / d out high z / d out x xxxv ih x x high z / d out high z / d out x xv ih x x x x high z / d out high z / d out x output disable v ih v il v ih v ih x x high z high z x v il v ih xxv ih v ih high z high z x v il v ih v ih v ih x x high z high z x product identification software mode v ih v il v il v ih x x manufacturer?s id (00bfh) device id 3 a 19 -a 1 =v il , a 0 =v ih (see table 4) t4.0 1267 1. do not apply bes#=v il and bef#=v il at the same time 2. x can be v il or v ih , but no other value. 3. with a ms -a 1 = 0; sst manufacturer?s id = 00bfh, is read with a 0 =0, sst32hf16xc device id = 234bh, is read with a 0 =1, sst32hf324c device id = 235bh, is read with a 0 =1
preliminary specifications multi-purpose flash plus + sram combomemory sst32hf162c / sst32hf164c / sst32hf324c 9 ?2004 silicon storage technology, inc. s71267-00-000 7/04 table 5: s oftware c ommand s equence command sequence 1st bus write cycle 2nd bus write cycle 3rd bus write cycle 4th bus write cycle 5th bus write cycle 6th bus write cycle addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 word-program 5555h aah 2aaah 55h 5555h a0h wa 3 data sector-erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h sa x 4 30h block-erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h ba x 4 50h chip-erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h 5555h 10h erase-suspend xxxxh b0h erase-resume xxxxh 30h software id entry 5,6 5555h aah 2aaah 55h 5555h 90h software id exit 7 /sec id exit 5555h aah 2aaah 55h 5555h f0h software id exit 7 /sec id exit xxh f0h t5.0 1267 1. address format a 14 -a 0 (hex). addresses a 15 -a 19 can be v il or v ih , but no other value, for command sequence for sst32hf16xc, addresses a 15 -a 20 can be v il or v ih , but no other value, for command sequence for sst32hf324c. 2. dq 15 -dq 8 can be v il or v ih , but no other value, for command sequence 3. wa = program word address 4. sa x for sector-erase; uses a ms -a 11 address lines ba x , for block-erase; uses a ms -a 15 address lines a ms = most significant address a ms = a 19 for sst32hf16xc and a 20 for sst32hf324c. 5. the device does not remain in software product id mode if powered down. 6. with a ms -a 1 =0; sst manufacturer id = 00bfh, is read with a 0 = 0, sst32hf16xc device id = 234bh, is read with a 0 = 1, sst32hf324c device id = 235bh, is read with a 0 = 1, a ms = most significant address a ms = a 19 for sst32hf16xc and a 20 for sst32hf324c. 7. both software id exit operations are equivalent
10 preliminary specifications multi-purpose flash plus + sram combomemory sst32hf162c / sst32h f164c / sst32hf324c ?2004 silicon storage technology, inc. s71267-00-000 7/04 absolute maximum stress ratings (applied conditions greater than t hose listed under ?absolute maximum stress ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater t han those defined in the operational sections of this data sheet is not implied. exposu re to absolute maximum stress rating co nditions may affect device reliability.) operating temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20c to +85c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65c to +150c d. c. voltage on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5v to v dd 1 +0.3v transient voltage (<20 ns) on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0v to v dd 1 +1.0v package power dissipation capability (ta = 25c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0w output short circuit current 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ma 1. v dd = v ddf and v dds 2. outputs shorted for no more than one second. no more than one output shorted at a time. o perating r ange range ambient temp v dd commercial 0c to +70c 2.7-3.3v extended -20c to +85c 2.7-3.3v ac c onditions of t est input rise/fall time . . . . . . . . . . . . . . 5 ns output load . . . . . . . . . . . . . . . . . . . . c l = 30 pf see figures 15 and 16
preliminary specifications multi-purpose flash plus + sram combomemory sst32hf162c / sst32hf164c / sst32hf324c 11 ?2004 silicon storage technology, inc. s71267-00-000 7/04 table 6: dc o perating c haracteristics (v dd = v ddf and v dds = 2.7-3.3v) symbol parameter limits test conditions min max units i dd active v dd current address input = v ilt /v iht, at f=5 mhz, v dd =v dd max, all dqs open read oe#=v il , we#=v ih flash 18 ma bef#=v il , bes#=v ih sram 30 ma bef#=v ih , bes#=v il concurrent operation 40 ma bef#=v ih , bes#=v il write 1 we#=v il flash 35 ma bef#=v il , bes#=v ih , oe#=v ih sram 30 ma bef#=v ih , bes#=v il i sb standby v dd current 30 a v dd = v dd max, bef#=bes#=v ihc i li input leakage current 1 a v in =gnd to v dd , v dd =v dd max i lo output leakage current 10 a v out =gnd to v dd , v dd =v dd max v il input low voltage 0.8 v v dd =v dd min v ilc input low voltage (cmos) 0.3 v v dd =v dd max v ih input high voltage 0.7 v dd vv dd =v dd max v ihc input high voltage (cmos) v dd -0.3 v v dd =v dd max v olf flash output low voltage 0.2 v i ol =100 a, v dd =v dd min v ohf flash output high voltage v dd -0.2 v i oh =-100 a, v dd =v dd min v ols sram output low voltage 0.4 v iol =1 ma, v dd =v dd min v ohs sram output high voltage 2.2 v ioh =-500 a, v dd =v dd min t6.0 1267 1. i dd active while erase or program is in progress. table 7: r ecommended s ystem p ower - up t imings symbol parameter minimum units t pu-read 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. power-up to read operation 100 s t pu-write 1 power-up to program/erase operation 100 s t7.0 1267 table 8: c apacitance (ta = 25c, f=1 mhz, other pins open) parameter description test condition maximum c i/o 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. i/o pin capacitance v i/o = 0v 12 pf c in 1 input capacitance v in = 0v 12 pf t8.0 1267 table 9: f lash r eliability c haracteristics symbol parameter minimum spec ification units test method n end 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. endurance 10,000 cycles jedec standard a117 t dr 1 data retention 100 years jedec standard a103 i lt h 1 latch up 100 + i dd ma jedec standard 78 t9.0 1267
12 preliminary specifications multi-purpose flash plus + sram combomemory sst32hf162c / sst32h f164c / sst32hf324c ?2004 silicon storage technology, inc. s71267-00-000 7/04 ac characteristics table 10: sram r ead c ycle t iming p arameters symbol parameter min max units t rcs read cycle time 70 ns t aas address access time 70 ns t bes bank enable access time 70 ns t oes output enable access time 35 ns t byes ubs#, lbs# access time 70 ns t blzs 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. bes# to active output 0 ns t olzs 1 output enable to active output 0 ns t bylzs 1 ubs#, lbs# to active output 0 ns t bhzs 1 bes# to high-z output 25 ns t ohzs 1 output disable to high-z output 0 25 ns t byhzs 1 ubs#, lbs# to high-z output 35 ns t ohs output hold from address change 10 ns t10.0 1267 table 11: sram w rite c ycle t iming p arameters symbol parameter min max units t wcs write cycle time 70 ns t bws bank enable to end-of-write 60 ns t aws address valid to end-of-write 60 ns t asts address set-up time 0 ns t wps write pulse width 60 ns t wrs write recovery time 0 ns t byws ubs#, lbs# to end-of-write 60 ns t odws output disable from we# low 30 ns t oews output enable from we# high 0 ns t dss data set-up time 30 ns t dhs data hold from write time 0 ns t11.0 1267
preliminary specifications multi-purpose flash plus + sram combomemory sst32hf162c / sst32hf164c / sst32hf324c 13 ?2004 silicon storage technology, inc. s71267-00-000 7/04 table 12: f lash r ead c ycle t iming p arameters v dd = 2.7-3.6v symbol parameter min max units t rc read cycle time 70 ns t ce chip enable access time 70 ns t aa address access time 70 ns t oe output enable access time 35 ns t clz 1 bef# low to active output 0 ns t olz 1 oe# low to active output 0 ns t chz 1 bef# high to high-z output 20 ns t ohz 1 oe# high to high-z output 20 ns t oh 1 output hold from address change 0 ns t12.0 1267 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. table 13: f lash p rogram /e rase c ycle t iming p arameters symbol parameter min max units t bp word-program time 10 s t as address setup time 0 ns t ah address hold time 30 ns t cs we# and bef# setup time 0 ns t ch we# and bef# hold time 0 ns t oes oe# high setup time 0 ns t oeh oe# high hold time 10 ns t cp bef# pulse width 40 ns t wp we# pulse width 40 ns t wph 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. we# pulse width high 30 ns t cph 1 bef# pulse width high 30 ns t ds data setup time 30 ns t dh 1 data hold time 0 ns t ida 1 software id access and exit time 150 ns t se sector-erase 25 ms t be block-erase 25 ms t sce chip-erase 50 ms t13.0 1267
14 preliminary specifications multi-purpose flash plus + sram combomemory sst32hf162c / sst32h f164c / sst32hf324c ?2004 silicon storage technology, inc. s71267-00-000 7/04 figure 2: sram r ead c ycle t iming d iagram figure 3: sram w rite c ycle t iming d iagram (we# c ontrolled ) 1 addresses a mss-0 dq 15-0 ubs#, lbs# oe# bes# t rcs t aas t bes t oes t blzs t olzs t byes t bylzs t byhzs data valid t ohzs t bhzs t ohs 1267 f02.0 note: a mss = most significant sram address a mss = a 16 for sst32hf162c and a 17 for sst32hf164c or sst32hf324c t aws addresses a mss 3 -0 bes# we# ubs#, lbs# t wps t wrs t wcs t asts t bws t byws t odws t oews t dss t dhs 1267 f03.0 note 2 note 2 dq 15-8, dq 7-0 valid data in note: 1. if oe# is high during the write cycle, t he outputs will remain at high impedance. 2. if bes# goes low coincident with or after we# goes low, the output will remain at high impedance. if bes# goes high coincident with or before we# goes high, the output will remain at high impedance. because d in signals may be in the output state at this time, input signals of reverse polarity must not be applied. 3. a mss = most significant sram address a mss = a 16 for sst32hf162c and a 17 for sst32hf164c or sst32hf324c
preliminary specifications multi-purpose flash plus + sram combomemory sst32hf162c / sst32hf164c / sst32hf324c 15 ?2004 silicon storage technology, inc. s71267-00-000 7/04 figure 4: sram w rite c ycle t iming d iagram (ubs#, lbs# c ontrolled ) 1 figure 5: f lash r ead c ycle t iming d iagram addresses a mss 3 -0 we# bes# t bws t aws t wcs t wps t wrs t asts t byws dq 15-8, dq 7-0 valid data in note 2 note 2 t dss t dhs ubs#, lbs# 1267 f04.0 note: 1. if oe# is high during the write cycle, t he outputs will remain at high impedance. 2. because d in signals may be in the output state at this time, input signals of reverse polarity must not be applied. 3. a mss = most significant sram address a mss = a 16 for sst32hf162c and a 17 for sst32hf164c or sst32hf324c 1267 f05.0 address a ms-0 dq 15-0 we# oe# bef# t ce t rc t aa t oe t olz v ih high-z t clz t oh t chz high-z data valid data valid t ohz note: a msf = most significant flash address a msf = a 19 for sst32hf16xc and a 20 for sst32hf324c
16 preliminary specifications multi-purpose flash plus + sram combomemory sst32hf162c / sst32h f164c / sst32hf324c ?2004 silicon storage technology, inc. s71267-00-000 7/04 figure 6: f lash we# c ontrolled p rogram c ycle t iming d iagram figure 7: bef# c ontrolled f lash p rogram c ycle t iming d iagram 1267 f06.0 address a ms-0 dq 15-0 t dh t wph t ds t wp t ah t as t ch t cs bef# sw0 sw1 sw2 5555 2aaa 5555 addr xxaa xx55 xxa0 data internal program operation starts word (addr/data) oe# we# t bp note: a msf = most significant flash address a msf = a 19 for sst32hf16xc and a 20 for sst32hf324c x can be v il or v ih, but no other value 1267 f07.0 address a ms-0 dq 15-0 t dh t cph t ds t cp t ah t as t ch t cs we# sw0 sw1 sw2 5555 2aaa 5555 addr xxaa xx55 xxa0 data internal program operation starts word (addr/data) oe# bef# t bp note: a msf = most significant flash address a msf = a 19 for sst32hf16xc and a 20 for sst32hf324c x can be v il or v ih, but no other value
preliminary specifications multi-purpose flash plus + sram combomemory sst32hf162c / sst32hf164c / sst32hf324c 17 ?2004 silicon storage technology, inc. s71267-00-000 7/04 figure 8: f lash d ata # p olling t iming d iagram figure 9: f lash t oggle b it t iming d iagram 1267 f08.0 addresses a msf-0 dq 7 data data# data# data we# oe# bef# t oeh t oe t ce t oes note: a msf = most significant flash address a msf = a 19 for sst32hf16xc and a 20 for sst32hf324c 1267 f09.0 addresses a msf-0 dq 6 and dq 2 we# oe# bef# t oe t oeh t ce t oes two read cycles with same outputs note: a msf = most significant flash address a msf = a 19 for sst32hf16xc and a 20 for sst32hf324c
18 preliminary specifications multi-purpose flash plus + sram combomemory sst32hf162c / sst32h f164c / sst32hf324c ?2004 silicon storage technology, inc. s71267-00-000 7/04 figure 10: we# c ontrolled f lash c hip -e rase t iming d iagram figure 11: we# c ontrolled f lash b lock -e rase t iming d iagram 1267 f10.0 address a ms-0 dq 15-0 we# sw0 sw1 sw2 sw3 sw4 sw5 5555 2aaa 2aaa 5555 5555 xx55 xx10 xx55 xxaa xx80 xxaa 5555 oe# bef# six-byte code for chip-erase t sce t wp note: this device also supports bef# controlled chip-erase operation. the we# and bef# signals are interchangeable as long as minimum timings are met. (see table 13) a msf = most significant flash address a msf = a 19 for sst32hf16xc and a 20 for sst32hf324c x can be v il or v ih, but no other value. note: a msf = most significant flash address a msf = a 19 for sst32hf16xc and a 20 for sst32hf324c this device also supports bef# controlled block-erase operation. the we# and bef# signals are interchangeable as long as minimum timings are met. (see table 13.) ba x = block address x can be v il or v ih, but no other value. 1267 f11.0 address a ms-0 dq 15-0 we# sw0 sw1 sw2 sw3 sw4 sw5 5555 2aaa 2aaa 5555 5555 xx55 xx50 xx55 xxaa xx80 xxaa ba x oe# bef# six-byte code for block-erase t be t wp
preliminary specifications multi-purpose flash plus + sram combomemory sst32hf162c / sst32hf164c / sst32hf324c 19 ?2004 silicon storage technology, inc. s71267-00-000 7/04 figure 12: we# c ontrolled f lash s ector -e rase t iming d iagram 1267 f12.0 address a ms-0 dq 15-0 we# sw0 sw1 sw2 sw3 sw4 sw5 5555 2aaa 2aaa 5555 5555 xx55 xx30 xx55 xxaa xx80 xxaa sa x oe# bef# six-byte code for sector-erase t se t wp note: a msf = most significant flash address a msf = a 19 for sst32hf16xc and a 20 for sst32hf324c this device also supports bef# controlled sector-erase operation. the we# and bef# signals are interchangeable as l ong as minimum timings are met. (see table 13.) sa x = sector address x can be v il or v ih, but no other value.
20 preliminary specifications multi-purpose flash plus + sram combomemory sst32hf162c / sst32h f164c / sst32hf324c ?2004 silicon storage technology, inc. s71267-00-000 7/04 figure 13: s oftware id e ntry and r ead figure 14: s oftware id e xit and r eset 1267 f13.0 address a 14-0 t ida dq 15-0 we# sw0 sw1 sw2 mfg id 5555 2aaa 5555 0000 0001 oe# bef# three-word sequence for software id entry t wp t wph t aa 00bf device id xx55 xxaa xx90 note: x can be v il or v ih, but no other value. device id - see table 2 on page 5 1267 f14.0 address a 14-0 dq 15-0 t ida t wp t whp we# sw0 sw1 sw2 5555 2aaa 5555 three-word sequence for software id exit and reset oe# bef# xxaa xx55 xxf0 note: x can be v il or v ih, but no other value.
preliminary specifications multi-purpose flash plus + sram combomemory sst32hf162c / sst32hf164c / sst32hf324c 21 ?2004 silicon storage technology, inc. s71267-00-000 7/04 figure 15: ac i nput /o utput r eference w aveforms figure 16: a t est l oad e xample 1267 f15.0 reference points output input v it v iht v ilt v ot ac test inputs are driven at v iht (0.9 v dd ) for a logic ?1? and v ilt (0.1 v dd ) for a logic ?0?. measurement reference points for inputs and outputs are v it (0.5 v dd ) and v ot (0.5 v dd ). input rise and fall times (10% ? 90%) are <5 ns. note: v it - v input te s t v ot - v output te s t v iht - v input high test v ilt - v input low test 1267 f16.0 to tester to dut c l
22 preliminary specifications multi-purpose flash plus + sram combomemory sst32hf162c / sst32h f164c / sst32hf324c ?2004 silicon storage technology, inc. s71267-00-000 7/04 figure 17: w ord -p rogram a lgorithm 1267 f17.0 start write data: xxaah address: 5555h write data: xx55h address: 2aaah write data: xxa0h address: 5555h write word address/word data wait for end of program (t bp , data# polling bit, or toggle bit operation) program completed note: x can be v il or v ih , but no other value
preliminary specifications multi-purpose flash plus + sram combomemory sst32hf162c / sst32hf164c / sst32hf324c 23 ?2004 silicon storage technology, inc. s71267-00-000 7/04 figure 18: w ait o ptions 1267 f18.0 wait t bp , t sce, or t be program/erase initiated internal timer toggle bit ye s ye s no no program/erase completed does dq 6 match? read same word data# polling program/erase completed program/erase completed read word is dq 7 = true data? read dq 7 program/erase initiated program/erase initiated
24 preliminary specifications multi-purpose flash plus + sram combomemory sst32hf162c / sst32h f164c / sst32hf324c ?2004 silicon storage technology, inc. s71267-00-000 7/04 figure 19: s oftware p roduct c ommand f lowcharts x can be v il or v ih, but no other value 1267 f19.0 load data: xxaah address: 5555h software product id entry command sequence load data: xx55h address: 2aaah load data: xx90h address: 5555h wait t ida read software id load data: xxaah address: 5555h software product id exit command sequence load data: xx55h address: 2aaah load data: xxf0h address: 5555h load data: xxf0h address: xxh return to normal operation wait t ida wait t ida return to normal operation
preliminary specifications multi-purpose flash plus + sram combomemory sst32hf162c / sst32hf164c / sst32hf324c 25 ?2004 silicon storage technology, inc. s71267-00-000 7/04 figure 20: e rase c ommand s equence 1267 f20.0 load data: xxaah address: 5555h chip-erase command sequence load data: xx55h address: 2aaah load data: xx80h address: 5555h load data: xx55h address: 2aaah load data: xx10h address: 5555h load data: xxaah address: 5555h wait t sce chip erased to ffffh load data: xxaah address: 5555h sector-erase command sequence load data: xx55h address: 2aaah load data: xx80h address: 5555h load data: xx55h address: 2aaah load data: xx30h address: sa x load data: xxaah address: 5555h wait t se sector erased to ffffh load data: xxaah address: 5555h block-erase command sequence load data: xx55h address: 2aaah load data: xx80h address: 5555h load data: xx55h address: 2aaah load data: xx50h address: ba x load data: xxaah address: 5555h wait t be block erased to ffffh note: x can be v il or v ih , but no other value.
26 preliminary specifications multi-purpose flash plus + sram combomemory sst32hf162c / sst32h f164c / sst32hf324c ?2004 silicon storage technology, inc. s71267-00-000 7/04 figure 21: c oncurrent o peration f lowchart 1267 f21.0 load sdp command sequence concurrent operation flash program/erase initiated wait for end of write indication flash operation completed end concurrent operation read or write sram end wait
preliminary specifications multi-purpose flash plus + sram combomemory sst32hf162c / sst32hf164c / sst32hf324c 27 ?2004 silicon storage technology, inc. s71267-00-000 7/04 product ordering information valid combinations for sst32hf162c SST32HF162C-70-4C-LBK SST32HF162C-70-4C-LBKe sst32hf162c-70-4e-lbk sst32hf162c-70-4e-lbke valid combinations for sst32hf164c sst32hf164c-70-4c-lbk sst32hf164c-70-4c-lbke sst32hf164c-70-4e-lbk sst32hf164c-70-4e-lbke valid combinations for sst32hf324c sst32hf324c-70-4c-lbk sst32hf324c-70-4c-lbke sst32hf324c-70-4e-lbk sst32hf324c-70-4e-lbke note: valid combinations are those products in mass producti on or will be in mass production. consult your sst sales representative to confirm availability of valid combinat ions and to determine availability of new combinations. package attribute e = non-pb package modifier k = 48 leads or balls package type lb = lbga (10mm x 12mm x 1.4mm) temperature range c = commercial = 0c to +70c e = extended = -20c to +85c minimum endurance 4 = 10,000 cycles read access speed 70 = 70 ns density 162 = 16 mbit flash + 2 mbit sram 164 = 16 mbit flash + 4 mbit sram 324 = 32 mbit flash + 4 mbit sram voltage h = 2.7-3.3v product series 32 = mpf + sram combomemory device speed suffix1 suffix2 sst32 h fxx xc - xxx -x x -xx x x
28 preliminary specifications multi-purpose flash plus + sram combomemory sst32hf162c / sst32h f164c / sst32hf324c ?2004 silicon storage technology, inc. s71267-00-000 7/04 packaging diagrams 48- ball l ow - profile b all g rid a rray (lbga) 10 mm x 12 mm sst p ackage c ode : lbk table 14: r evision h istory number description date 00 initial release jul 2004 h g f e d c b a a b c d e f g h bottom view side view 6 5 4 3 2 1 seating plane 0.40 0.05 1.4 max 0.12 0.50 0.05 (48x) 1.0 5.0 1.0 7.0 48-lbga-lbk-10x12-500mic-2 note: 1. although many dimensions are similar to those of jedec publication 95, mo-210, this specific package is not registere d. 2. all linear dimensions are in millimeters. 3. coplanarity: 0.12 mm 4. ball opening size is 0.4 mm ( 0.05 mm) 6 5 4 3 2 1 1mm top view 10.00 0.20 12.00 0.20 a1 corner a1 corner silicon storage technology, inc. 1171 sonora court sunnyvale, ca 94086 telephone 408-735-9110 fax 408-735-9036 www.superflash.com or www.sst.com

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